1. Field of the Invention
The disclosure relates to a semiconductor memory device and, more particularly, to a semiconductor memory device that can perform a write operation faster than a read operation, and a data read and write method of the same.
2. Description of the Related Art
A conventional double data rate (DDR) semiconductor memory device is divided into three types; DDR1, DDR2, and DDR3, each with a maximum operating frequency of 400 MHz, 800 MHz, and 1 GHz. respectively.
In the conventional DDR semiconductor memory device, during a write operation and a read operation, a minimum column selecting cycle time is set to one clock cycle for DDR1, two clock cycles for DDR2, and four clock cycles for DDR3. Here, the minimum column selecting cycle time is referred to as a minimum cycle time that a continuous write operation or a continuous read operation can be applied.
In general, the DDR2 semiconductor memory device is faster in operation speed than the DDR1 semiconductor memory device, and the DDR3 semiconductor memory device is faster in operation speed than the DDR2 semiconductor memory device. However, there is a problem in that the DDR3 semiconductor memory device is slower in operation speed than the DDR2 semiconductor memory device during a low frequency operation within an operable frequency range of the DDR3 semiconductor memory device. Similarly, the DDR2 semiconductor memory device may be slower in operation speed than the DDR1 semiconductor memory device.
For example, the operable frequency range of the DDR3 semiconductor memory device is larger than 800 MHz and equal to or lower than 1 GHz. When a minimum column selecting cycle time is equally set to four clock cycles at a frequency of 850 MHz during a write operation and a read operation of the DDR3 semiconductor memory device, an operation performance of the DDR3 semiconductor memory device is deteriorated compared to the DDR2 semiconductor memory device, because the clock frequency is in the lower range within the operating frequency of a DDR3 memory of 800 MHz to 1 GHz.
Meanwhile, a read operation has a lower frequency margin than that of a write operation. Therefore, there is a need to improve an operation performance of the DDR3 semiconductor memory device by maintaining a minimum column selecting cycle time to four clock cycles during a read operation and by making a minimum column selecting cycle time smaller than four clock cycles during a write operation, at a low frequency within an operable frequency range.
Similarly, there is a need to improve an operation performance of the DDR2 semiconductor memory device by maintaining a minimum column selecting cycle time to two clock cycles during a read operation and by making a minimum column selecting cycle time smaller than two clock cycles during a write operation.